A flash memory uses nonvolatile memory elements each having a control gate and a floating gate similar to FAMOSs, as its memory cells, and each memory cell can be constructed of one transistor. In such a flash memory, for a programming operation, the drain voltage of the nonvolatile memory element is set to about 5 V, as shown in FIG. 12, and the word line connected to the control gate is set to about -10 V, so that the charge on the floating gate is drawn therefrom by tunnel current to set the threshold voltage to a low value (logic "0").
For the erasing operation, as shown in FIG. 13, the P-type semiconductor region pwell is set to about -5 V, and the word line is set to about 10 V, so that tunnel current is caused to flow to inject negative charges into the floating gate, thereby to set the threshold value to a high state (logic "1"). Thus, one memory cell is able to store the data of one bit.
Incidentally, there has been the concept of a so-called "multi-value" memory has been proposed in which data of two or more bits are stored in one memory cell so as to increase the storage capacity. An invention relating to such a multi-value memory is disclosed in Japanese Patent Laid-Open No. 121696/1984.
In a flash memory of the prior art, it is known that the variation of the threshold value is increased due to both a weak program (the disturb) or the like caused by the programming, reading and erasing operations of an adjacent bit and natural leakage (the retention), and consequently, the half-value width (the width of the peak of the bell-shaped variation distribution at the position of a half peak value, as shown in FIG. 3) of the variation distribution of the threshold value corresponding to logic "0" and "1" increases with the lapse of time. The inventors have found that, with the lower level of the power supply voltage of future LSIs, the threshold voltage of the memory cells may exceed the marginal range for the read voltage by the broadening of the variation distribution with time, thereby to cause a malfunction.
This problem is especially serious in a multi-value memory for storing one memory element with data of a plurality of bits by the difference between the threshold values, because this difference is small for the individual data. In a flash memory, moreover, there is a technical problem for minimizing the processing time and the circuit scale intrinsic to the multi-value memory, because of the erasing and program verifying operations intrinsic to the nonvolatile memory device.
An object of the present invention is to provide a multi-value type nonvolatile memory device which can realize programming, reading and erasing operations of high accuracy performed in a short time while minimizing the increase in the circuit scale.
Another object of the present invention is to provide a method of sharpening the shape of the variation distribution of the threshold values, and accordingly, a nonvolatile memory device capable of stably operating at a low voltage.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representative features of the invention to be disclosed herein will be briefly summarized in the following.
(1) At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element in a selected state, so that it is brought into a state in which it has a threshold value corresponding to the multi-value data. In the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by an inverse data transforming logic circuit on the basis of the multi-value data stored in the register.
(2) After a weak erasing operation of the memory elements in the memory array has been executed, the memory element, which has a threshold value lower than the read level of the word line and higher than the verify level, is detected, and the program is executed such that the threshold value of the memory element may be lower than the verify voltage thereby to narrow the width of the variation distribution shape of the threshold voltage of the memory element which is programmed correspondingly to the individual input data.
According to the aforementioned feature (1), the peripheral circuit scale of the memory array can be suppressed to a relatively small size. In the programming operation, the verify voltage value of the word line is sequentially changed (as will be seen in (1) to (4) of FIG. 3) by a predetermined value in a direction away from the near side of the erasing word line voltage, so that the total number of the program pulses, i.e., the program time, can be made shorter than that of the multi-value flash memory system, in which the verify voltage is set at random, thereby to realize a programming operation performed in a short time.
According to the aforementioned feature (2), on the other hand, the shape of the variation distribution of the threshold voltage of the memory elements, which has been widened due to disturb or retention influences, can be returned to a steep shape substantially identical to that just after the end of the programming operation.